1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit and a semiconductor integrated circuit manufactured thereby and, more particularly, to a method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and a semiconductor integrated circuit manufactured thereby.
2. Description of Related Art
Metal-Oxide-Semiconductor (MOS) transistors exhibit various advantages as compared to bipolar transistors. For example, the MOS transistors are suitable for a semiconductor integrated circuit (IC) having a high integration density and a low operation voltage with low power consumption. Therefore, most semiconductor ICs employ the MOS transistors as switching elements.
As semiconductor ICs have become more highly integrated, MOS transistors have been scaled down. As a result, the electrical characteristics and reliability of such semiconductor ICs are sometimes degraded thereby causing malfunctions. For example, attempts to increase device integration density in semiconductor ICs have typically resulted in reduction of the widths of gate electrodes of MOS transistors and in the reduction of junction depths of source/drain regions thereof. In such devices, electrical resistances of the gate electrodes and the source/drain regions are increased, and the reliability (for example, hot carrier effect and short channel effect) and the electrical characteristic.(for example, signal delay time) of the MOS transistors can be degraded. In order to solve these problems, a self-aligned silicide (SALICIDE) technique and a lightly doped drain (LDD) structure have been widely used in fabrication of MOS transistors. Gate spacers are generally formed on the sidewalls of the gate electrodes in order to realize the LDD-type source/drain structure and the SALICIDE technique.
The fabrication technology of the semiconductor ICs having the gate spacers is taught in U.S. Pat. No. 6,043,537 to Jun et al., entitled “Embedded memory logic device using self-aligned silicide and manufacturing method therefore.”
The manufacturing method of semiconductor devices according to the U.S. Pat. No. 6,043,537 includes preparing a semiconductor substrate that has a DRAM cell array region and a peripheral circuit region. Active regions are formed at the semiconductor substrates. Word lines and gate electrodes are formed in the DRAM cell array region and the peripheral circuit region, respectively. The word lines are formed to extend across the active regions in the DRAM cell array region, and the gate electrodes are formed to extend across the active regions in the peripheral circuit region. Impurity ions are then implanted into the active regions using the word lines and the gate electrodes as ion implantation masks, thereby forming low concentration source/drain regions. As a result, first and second low concentration source regions as well as a common low concentration drain region are formed at the respective active regions in the DRAM cell array region. The first and second low concentration source regions correspond to storage node junctions of DRAM cells.
A conformal spacer layer is formed on an entire surface of the semiconductor substrate having the low concentration source/drain regions. A photoresist pattern is formed on the spacer layer. The photoresist pattern is formed over the first and second low concentration source regions. The spacer layer is anisotropically etched using the photoresist pattern as an etch mask. Accordingly, spacers are formed on the sidewalls of the word lines and the gate electrodes. However, the conformal spacer layer on the first and second low concentration source regions is not anisotropically etched due to the photoresist pattern. Therefore, spacer layer patterns acting as salicide blocking patterns are formed on the first and second low concentration source regions. After removing the photoresist pattern, impurity ions are implanted into the active regions using the word lines, the gate electrodes, the spacers and the salicide blocking patterns as ion implantation masks, thereby forming high concentration source/drain regions. As a result, LDD-type source/drain regions are formed in the active regions of the peripheral circuit regions, and LDD-type common drain regions are formed in the active regions of the DRAM cell array region.
Subsequently, a metal layer is formed on an entire surface of the semiconductor substrate having the LDD-type source/drain regions, and the metal layer is annealed to form a metal silicide layer. As a result, the metal silicide layer is selectively formed on the word lines, the common drain regions, the gate electrodes and the source/drain regions in the peripheral circuit region. In other words, the metal silicide layer is not formed on the storage nodes, i.e., the first and second low concentration source regions.
Eventually, according to the U.S. Pat. No. 6,043,537, the leakage current that flows through the storage node junctions can be reduced.
In addition, spacers are widely used in fabrication of self-aligned contact holes. In this case, the spacers are formed of an insulating layer (for example, a silicon nitride layer) having an etching selectivity with respect to a conventional interlayer insulating layer.
However, if spaces between interconnection lines such as the word lines are reduced, actual areas of the source/drain regions exposed by the self-aligned contact holes are greatly reduced because of the presence of the spacers.